Manufacturing of integrated circuits is generally a procedure of forming thin films and layers of various materials on wafers of base semiconductor material, and selectively removing areas of such films to provide structures and circuitry. Doped silicon is a typical base wafer material. CVD is a well known process for epositing such thin films and layers. For example, polysilicon may be deposited from silane gas, SiH.sub.4. It is known, too, to deposit tungsten silicide from a mixture of gases including silane and a tungsten-bearing gas such as tungsten hexaflouride. Pure tungsten is also deposited on silicon wafers in the manufacture of integrated circuits, sometimes selectively and sometimes across the entire surface in a process known as "blanket" tungsten.
In a typical CVD process such as blanket tungsten wafers are placed on supports within a sealable chamber, the chamber is sealed and evacuated, the wafers are heated, typically by heating the wafer support, and a gas mixture is introduced into the chamber. For example, in the blanket tungsten process, tungsten hexaflouride and hydrogen are introduced as reactive gases, and typically argon is introduced as a non-reactive carrier gas. The tungsten hexaflouride is the source of deposited tungsten. Typically the gases are flowed continuously during process. The temperature of a substrate (wafer) to be coated is one of the variables that drives the chemical reaction to cause tungsten to be deposited on the substrate surface. It is important to control the temperature, the concentration of various gases in the mixture introduced, and such characteristics as the uniformity of flow of gas over the surface being coated, among other variables. An even thickness of a deposited layer is an important characteristic.
In most cases, active structures and circuitry are formed on one side of a wafer, and the other side is not so used. The side not so used is called the backside of the wafer. In lithography procedures for defining patterns on deposited layers to aid in the proper selective removal of such deposited layers to form structures and circuitry, the backside of a wafer is typically used as a registering surface. For this and other reasons it is important that the backside of a wafer be kept smooth and clean, and that material not, in general, be deposited on the backside.
Another important characteristic in layering techniques is that the deposited layers be adherent to the base wafer material or to the next underlying layer, so layered material doesn't flake or peel. The dimensions of structures and circuitry in integrated circuit technology are very small, so any unwanted flaking or peeling may easily cause particles that may spoil structures or circuitry. Moreover, flakes from non-adherent material can spoil structures and circuitry on other wafers, and also may damage sensitive equipment and require cleaning procedures beyond those that might otherwise be necessary.
Several techniques are employed to enhance adhesion of layers deposited by CVD. One is to deposit a thin layer of a material known as an adhesion layer or a glue layer. An adhesion layer in some cases is an entirely different material known to be adherent to the base material and to the material of a new layer to be applied. An adhesion layer is also sometimes applied in a separate process other than CVD. For example, titanium is in some cases deposited by sputtering as an adhesion layer before depositing tungsten or a tungsten rich material, such as tungsten silicide, by chemical vapor deposition. Cleaning procedures, such as ion bombardment, are also used to prepare wafer surfaces to receive layers deposited by chemical vapor deposition.
For logistic reasons it is generally desirable to do pretreatment steps, such as ion cleaning, and to deposit adhesion layers, while a wafer is mounted in the same chamber and upon the same apparatus that will be used to perform the chemical vapor deposition. Otherwise the wafers to be coated have to be handled more often and mounted to and dismounted from different processing apparatus, which is time consuming and expensive, and increases the chances of damage, error, and contamination. Since the wafers are typically mounted in the CVD chamber with the backside against a support, only the frontside is presented to process steps designed to enhance adhesion. If only the frontside is cleaned or otherwise treated, the probability of subsequent coating on the backside or edge becomes greater.
The surfaces of wafers to be coated commonly exhibit a varying topography due to devices formed on the wafers, circuitry previously etched, and layers previously coated. These variations in topography are manifested typically in grooves (vias) and holes of varying depth in the surface, and it is important to be able to deposit films of relatively uniform thickness into such surface depressions, or in many cases, to fill the depressions completely.
FIG. 1A shows a section of a wafer 11 through an idealized via with a coating 13 to illustrate how coverage in vias and holes is quantified in the art. The severity of a via or hole is called Aspect Ratio (AR), and is the depth D.sub.1 divided by the width D.sub.2. EQU AR=D.sub.1 /D.sub.2
Step coverage in a surface depression is quantified as a fraction or percentage determined by the minimum thickness D.sub.3 of the film formed in the depression divided by the nominal thickness D.sub.4 outside the via or hole. Typically, if coating conditions such as temperature and pressure remain constant, the step coverage degrades for most coating processes as the Aspect Ratio increases. Such degradation is more severe for line-of-sight processes like plasma sputtering than for CVD processes.
The trend of technical developments in the art of manufacturing integrated circuits is to greater and greater aspect ratio. One reason is that desirable increased density of devices and circuits on a single chip results in individual features being closer and closer together. Another reason is that manufacturers have developed multi-layering techniques wherein circuitry is built up in layers to make efficient use of surface area, and deep vias must be etched so that electrically conductive layers can be deposited to connect devices in different layers.
As device dimensions have decreased to typical dimensions under one micron, the coating thickness requirements have not decreased proportionally. The result is a situation depicted by FIG. 1B. Narrower and deeper depressions in the topography of a wafer, without decreasing coating thickness, causes closing of the depression by the coating. The situation shown in FIG. 1B is but one of many possibilities, and illustrates a serious flaw that can result. The closing of the depression by the coating can leave a pocket 14 beneath the closed coating surface. The pocket is generally detrimental to function and reliability. Hole filling is quantified by the decimal or percentage: 2.times.D3/D2. 1 (or 100%) represents complete hole filling.
FIG. 1C shows a situation similar to that of FIG. 1B, except the depression has been completely filled, leaving no trapped pocket below the surface. Complete hole filling as shown in FIG. 1C is the only acceptable condition for reliable process when hole filling is required at all.
Experience in coating devices with topography having smaller and smaller device geometry and larger and larger aspect ratios has shown that there is a relationship between the pressure of the process gases during CVD processing and the ability to coat evenly into vias and holes, and to do complete hole filling. In general, as pressure increases, step coverage and hole filling improve, pass through a maximum point, and then decrease again. The maximum point has a temperature dependence, and the inventors have seen the maximum vary from 10 to 80 Torr total pressure. FIG. 1D is a three-dimensional plot showing how hole filling is effected by pressure and temperature in the apparatus of the present invention. The trend is believed to be similar for CVD equipment in general.
In addition to generally better step coverage and hole filling at higher pressures, up to a point, higher pressure also typically provides a generally higher deposition rate, increasing throughput and decreasing operating costs per wafer coated. These expected advantages have made higher pressure operation very desirable in processes like blanket tungsten, but the tendency to backside coating caused by higher pressure operation has, up until the present invention, made the high pressure operations difficult and generally impractical. Blanket tungsten, for example, has typically been done at a total process pressure below 1 Torr.
Processes today are being done with total process pressures of 30 Torr and more, and processes are contemplated with total process pressures much higher; perhaps 80 to 100 Torr. An upper limit is not known at this time. What is needed is apparatus and method to allow these much higher process pressures while excluding coating gases from the edge and backside of wafers in process.